The invention relates to a bi-polar transistor and a procedure for its manufacture.
An important domain of use of vertical bi-polar transistors are high-speed applications. In order to improve the efficiency of transistors in the domain of highest speeds, the influence of parasitic components, i.e., resistance and capacitance, must be reduced. Therefore, highly conductive connections between the metal contacts and the active (inner) transistor region as well as a minimized passive transistor surface are required.
In order to meet these requirements, laterally scaled, the so-called xe2x80x9cdouble polysilicon technologiesxe2x80x9d are used in modem procedures to manufacture vertical bi-polar transistors. Such technologies make it possible to arrange the base contact and parts of the highly conductive polysilicon connection between the contact and the inner base through insulated zones. However, these design advantages as compared with the xe2x80x9csimple polysilicon technologiesxe2x80x9d are associated with such disadvantages as additional process complexity and increased contact resistance. These disadvantages arise in connection with the required etching of the polysilicon in the active zone of the transistor, and the diffusion of the doping agents from the highly doped polysilicon layer into the monocrystal base zone. Since the polysilicon for the base is removed over the active transistor zone by means of a dry-etching procedure, and there is no selectivity to the underlying monocrystal silicon, damage occurs to the exposed silicon surface. The consequence is then roughness of the surface, imperfections of the grid structure and penetration of foreign substances. Various procedures have been suggested to eliminate these problems. For example, etching-stop layers are used to protect the emitter zone in order to resolve the problems with dry etching. Additional procedure and cost is required to guarantee the self-adjusting of,the emitter zone and the etching-stop layer.
The application of epitaxy processes has recently further improved the high-speed properties. In-situ doping is used during the deposition in order to achieve smaller sizes of the base, i.e., smaller thickness of the base layer and smaller base layer resistance. An additional variance in achieving a certain resistance of the base layer and a current gain and, therefore, optimal high-speed properties is provided by the deposition of heterogeneous layers.
The concept of the double polysilicon technology with an etching-stop layer is also applied in the case of an epitaxially deposited base layer using the so-called selective epitaxy. During the selective epitaxy process, the deposition conditions are such that the epitaxial growth occurs only on uncovered semiconductor surface. If differential epitaxy is used, during which the silicon material is deposited both on the semiconductor and the insulator zones, an inner base and the connection to a base contact (base zone) located on the insulator zone can be produced at the same time. This generally eliminates the need of an additional polysilicon layer. The resulting quasi double polysilicon arrangement allows to simplify the process.
However, as compared with a full-fledged double polysilicon process we face a disadvantage consisting in the fact that the thickness of the epitaxy layer in the active transistor zone cannot be set independently from the thickness of the silicon layer in the base zone or on the insulator zones. Due to the insufficient nucleation of the SiO2 layer usually used as insulator, the polycrystal layer is usually thinner than the epitaxially grown layer. As for the epitaxy layer thickness, two different requirements exist. Within the emitter zone, a sufficiently thin layer should be present between the highly doped emitter and the base. A thicker layer is beneficial in the outer base zone to allow low resistance of the base. The patent documentation U.S. Pat. No. 5,137,840A describes differential epitaxy process in a UHVCVD system at a pressure between 1xc3x9710xe2x88x924 and 1xc3x9710xe2x88x922 Torr and a constant deposition temperature of 500-800xc2x0 C. for the buffer layer.
The task of this invention is to propose a bi-polar transistor and a procedure for its manufacture that eliminates the disadvantages of conventional arrangements for a simple polysilicon technology with differential epitaxy for the manufacture of the base, in order to further improve especially the high-speed properties of a bi-polar transistor, to produce highly conductive connections between the metal contacts and the active (inner) transistor region as well as a minimized passive transistor surface, and to simultaneously avoid any additional process complexity and increased contact resistance.
This invention resolves the task in that, by creating suitable epitaxy process conditions, the polysilicon layer is deposited on the insulator zone with a greater thickness than the epitaxy layer in the active transistor zone. The greater thickness of the polysilicon layer as compared to the epitaxial layer is achieved by using a very low temperature for the deposition of a part of or the entire buffer layer. Apart from using a polysilicon layer, this invention also includes the possible use of an amorphous silicon layer. The use of a low temperature for the deposition allows a better nucleation of the insulator layer and a reduction of the idle time for the deposition. The deposition at a very low temperature allows a higher deposition rate for the polycrystal or amorphous layer as compared with the epitaxial layer. This allows achieving a greater thickness on the insulator layer as compared with the active transistor zone.
A simple polysilicon bi-polar transistor with an epitaxially made base according to this invention allows a reduction of the outer base resistance without having to accept a deterioration of the emitter properties. Due to a continuous deposition of the inner and outer zones no surface problems occur with the base.